TCM 3105 PAGE 1 (4-5)
FSK MODEM
DUAL IN IHE PACKAGE
Features
(TOP VIEW)
Single chip FSK modem. �����Ŀ
Meets CCITT V23 standard: VDD �1��� � OSC2
- Forward channel (Transmit/Receive) CLK � � 0SC1
at 600/1200 bauds CDT � � TXD
- Backward channel (Transmit/Receive) RXA � � TXR1
at 75 bauds. TRS � � TXR2
Meets Bell 202 standards: RXT � � TXA
- Forward channel (Transmit/Receive) RXB � � CDL
at 1200 bauds RXD �8 9� VSS
- Backward channel(Transmit/Receive) �������
at 5/150 bauds. TCM3105J OR TCMJ105N
Full duplex operation up to 1200 bauds
Transmit and receive in 4 wire mode.
Carrier detect level adjustment and carrier
fail output.
SURFACE MOUNT SMALL OUTLINE PACKAGE
On chip Transmit/Receive filtering and (TOP VIEW)
group delay equalisation. �����Ŀ
Reliable CMOS silicon gate technology. VDD �1 24� OSC2
16 pin DIL package (pin to pin CLK � � 0SC1
compatible with TCM 3101 ). CDT � � TXD
Local copy/loop back test capability. � �
RXA � � TXR1
� �
TRS � �
� � TXR2
RXT � � TXA
� �
RXB � � CDL
RXD �12 13� VSS
�������
TCM3105DW
TCM 3105 PAGE 2 (4-6)
FSK MODEM
general description
The TCM3105 is a versatile single chip Frequency Shift Keyed (FSK) voiceband
modem. It uses silicon gate CMOS technology with switched capacitor filtering
techniques.It is pin programmable (using V23 operation and is fully reversible,
thereby allowing both forward and backward channels to be used simultaneously).
The transmitter is a programmable frequency synthesizer which provides two
output frequencies (on TXA), representing the "Marks" and "Spaces" ot the
digital signal present on the TXD input.
The receive section is responsible tor the demodulation ot the analogue signal
appearing at the RXA input and is based on the principle of frequency to
voltage conversion. This section contains a Group Delay Equaliser (to correct
phase distortion). Automatic Gain Control, Carrier Detect Level adjustment and
Bias Distortion adjustment, thereby optimising performance and giving the
Iovest possible bit error rate.
Carrier detect intormation is given to the system by means ot the carrier
detect circuitry which sets a flag on the CDT output if the level ot received
in band energy falls below a value set on the CDL input for a specified minimum
duration.
DW NorJ
PACK PACK SYMBOL DESCRIPTION
PIH N PIH N
1 1 VDD Positive supply voltage
2 2 CLK A continuous clock signal output
3 3 CDT Carrier Detect Output. A low level output indicates
carrier fail
5 4 RXA Receive analogue input. The received line signal must
be a.c. coupled to RXA pin
7 5 TRS Transmit Receive standard select. This pin, together
with TXR1 and TXR2 set the standar bit rates and
mark space frequencies (see fig. 5)
9 6* RXT Receive Test access. The output of the limiter is
available on this pin
11 7 RXB Receive bias adjust. External adjustment of the
decision threshold of the final comperator to minimise
bias distortion is avaiiable
12 8 RXD Receive digital output. The demodulated receved data in
positive true logic, logic one is a mark and logic zero
a space
13 9 VSS Negative supply voltage, normally ground, connected to
substrate
14 10 CDL Carrier detect level adjust. External adjustment of
carrier detect threshold is available
16 11 TXA Transmit analogue output. This is the modulated signal
and must be a.c. coupled
17 12 TXR2 Bit rate select. These tow pins, together with TRS set
the bit rates and mark space frequencies
20 13 TXR1 (see fig. 5)
22 14 TXD Transmit digital input. The input data to the
transmitter must be possible true logic. Logic one is a
mark, logic zero is a space. The data can be accepted
at any speed from zero to the selected speed
and may be totally asynchronous
23 15 OSC1 Oscillator connections. The crystal typically 4.4336
MHz PAL is connected to these pins if an
24 16 OSC2 external clock is used OSC2 is left open circuit and
the clock connected to OSC1
Pins N 4/6/8/10/15/18/19/21 are connected for the DW package.
*Not connected for TCM3105J and TCM3105JE
TCM 3105 PAGE 3 (4-7)
FSK MODEM
TCM 3105 Block Diagram
FIG.1 See 3105_1.sch (OrCAD SDT schematic file)
absolute maximum ratings
Supply voltage VDD 0.3 - 10V
Voltage cn any terminal 0.3 - VDD
Operating free air temperature range -20...+70 C
Storage temperature range -55..+150 C
Any Input relative to VDD +0.3V
Any Input relative to VSS -0.3V
Unless otherwise stated, all voltages are with respect to VSS. Stresses
beyond those listed under "absolute maximum ratings" may cause permanent
damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions beyond indicated in the
"recommended operating conditions" section of this specification is not
implied. Exposure to absolute maximum rated conditions for extended periods
may affect device reliability.
TCM 3105 PAGE 4 (4-8)
FSK MODEM
recommended operating conditions
PARAMETER MIN TYP MAX UNIT
VDD supply voltage 4 5 6 V
Digital input levels: VIH VDD<5.5V 2.0 VDD V
5.5V<VDD<6V 2.4 VDD V
VIL VSS 0.8 V
VRXA analog input level (a.c. coupled) 0.78 V PK-PK
Master clock frequency (quartz PAL) 3.4330 4.4336 4.4340 MHz
Operating free air temperature range -20 70 deg C
Analog load impedance at TXA 50 kohm
electrical characteristics
Over recommended operating free-air temperature range (-20 to 70 C)
PARAMETER TEST MIN TYP MAX UNIT
CONDITIONS L E*
IDD supply current VDD = 4V 3 4 6 mA
VDD = 5V 5.5 8 10 mA
VDD = 6V 8 12 16 mA
IID digital input current VSS<=VIN<=VDD 1.0 uA
IIA analog input current 10 uA
Digital output level VOH IOH = 100uA 2.4 VDD V
VOL IOL = 1.6mA VSS 0.5 V
Analog output level VDD = 4V 1.1 1.55 1.9 V PK-PK
VTXA (p-p)= VDD = 5V 1.9 V PK-PK
0.76 VDD/2 VDD = 6V 1.7 2.3 2.9 V PK-PK
RL=50Kohm
CL=100pF
Analog output dc offset VDD/2 V
Input capacitance f = 1MHz 15 pF
Output capacitance f = 1MHz 15 pF
Carrier detect treshold CTHH(Off-On) -45.5 -43 dBm
CTHL(On-Off) -48 -45.5 dBm
CTHH-CTHL 2 2.5 5 dB
Carrier detect delay
Rx = 600 or 1200 bps TD Off-On 12 20 ms
TD On-Off 12 16 ms
Rx = 5.75 or 150 bps TD Off-On 48 80 ms
TD On-Off 48 60 ms
* TCM3105N/3105DW/3105JL are specified at -20 C...+70 C
TCM3105JE is specified at -40 C...+85 C
TCM 3105 PAGE 5 (4-9)
FSK MODEM
functional description
A. PIN DESCRIPTION
Transmitter Digital Input (TXD)
The data to be transmitted is presented to this input. The data should be
positive true logic, a logic "1" being a mark and a logic "0" a space.
This data may be totally asynchronous and has no speed restriction.
A data rate from zero to the transmit speed selected is acceptable.
Transmitter Analogue Output (TXA)
The output of the FSK modulaled signal appears on this pin.
The voltage swing of this analogue signal is dependent on the power supply.
This output signal is referred to the internal reference voltage and hence
TXA must be a.c. coupled.
Receive Transmit Mode Select Inputs (TXR1, TXR2, TRS)
The logic state of these inputs is internally decoded to place the modem
into the required mode. A transmitter disable mode is also available.
Pin TRS is effectively a three state input, since it can receive a high level
(1), a low level (0) or the clock output (CLK) See fig.5 for possible modes.
Receiver Analogue Input (RXA)
The modulated analogue signal is received at this pin. Due to the single supply
of the TCM3105, this input is internally biased by an internal reference
voltage and must be a.c. coupled.
Receiver Digital Output (AXD)
This output provides the demodulated received data in positive true logic,
a received mark frequency being a "1" and a received space frequency a "0".
Receiver Bias Adjust Input (RXB)
This input allows external adjustment of the decision threshold of the final
comparator stage and hence the bias distortion of the output data.
This adjustment is independent of the receive mode.
Carrier detector Output (CDT)
This output provides a carrier detect flag for the system.
A high logic level signals the presence of in-band energy for a time longer
than the minimum specified duration and a low level signals the absence of
in-band energy for a time longer than the minimum specified duration.
Carrier Detect Level Adjust Input (CDL)
This input allows external adjustment of the carrier level threshold via an
external potentiometer.
Clock Oscillator Input/Output (OSC1, OSC2)
These pins are the input and output of the on-chip clock oscillator and are
typically connected to a 4.4336 MHz PAL quartz crystal. An external clock may
be used by connecting it to OSC1 and leaving OSC2 open circuit.
Clock Output (CLK)
This output provides a continous clock signal at 16 times the highest selected
(transmit or receive) bit rate. This clock is intended for external use such as
UART control and as an input signal of the TRS input after a correct division
(See Fig. 5 for possible modes).
Receiver Test Output (RXT)
This output is an intermediate limiter output.
Power Supply Inputs (VDD,VSS)
The pins VDD and VSS must be connected to the correct voltage supplies.
VDD is the positive supply as specified and VSS is the negative supply voltage,
normally ground, which is connected to the substrate.
TCM 3105 PAGE 6 (4-10)
FSK MODEM
B. CIRCUIT DESCRIPTION
The TCM3105 modem is made up of four functional blocks - Transmitter
- Receiver
- Carrier Detector
RXT RXB - Timing and Control
� �
^ �
������������������������Ŀ
RXA>����Ĵ RECEIVER ��������>RXD
� ��������������������������
� �
� ^ ��������������<CDL
� � �
� ������������������������Ŀ
�Ĵ CARRIER DETECTOR ��������>CDT
��������������������������
�
^ ���������������������<TXR1,TXR2,TRS
� �
������������������������Ŀ
CLK<����Ĵ TIMING & CONTROL ��������<MASTER CLOCK
��������������������������
V
������������������������Ŀ
TXA<����Ĵ TRANSMITTER ��������<TXD
��������������������������
FIG.2
transmitter
The transmitter comprises a phase coherent FSK modulalor, transmit filter and
transmit amplifier (fig 3). The modulator is a programmable frequency synthesi-
ser which derives the output frequencies by variable division of the 4.4336 MHZ
Master Clock Frequency. The division ratio is set by the state of the transmit
receive standard pin (TRS). The transmit bit rate pins (TXR1 and TXR2) and the
data input (TXD).
The frequencies are given in fig. 6 and the data convention is "1" equals mark
and "0" equals space.The final stage of the Transmitter section is the
Transmit filter followed by the Transmit amplifier.
TRANSMITTER
�TXR1,TXR2,TRS
����������������Ŀ
V V
� �����������Ŀ �����Ŀ
��������������Ŀ � TRANSMIT � � �
TXD>�����Ĵ MODULATOR ��>Ĵ ��>�Ĵ AMP �����>TXA
���������������� � FILTER � � �
������������� ������� FIG.3
The frequency response of the transmit filter is dependent upon the mode
selected on the TRS, TXR1, TXR2 inputs. In all modes, the first filter section
is a switched capacitor low-pass filter which limits the level of harmonics at
its output. (This filter has a switching frequency response which provides
optimum characteristics for each transmit frequency). For the 75 150 bauds
receive mode and 600 1200 bauds transmit mode, the output of the switched
capacitor low-pass filter is applied in turn, to an antialiasing filter, a
switched capacitor high-pass filter and equaliser before passing through a
smoothing filter, the output of which is the TXA pin. This suppresses receive
band frequencies such that they do not appear at TXA.
For the 600 1200 bauds receive mode, the output of the switched capacitor
low-pass filter is applied to a continous low-pass filter, in order to remove
harmonics due to sampling, before outputting the signal on TXA.
TCM 3105 PAGE 7 (4-11)
FSK MODEM
receiver
The demodulation function of the receiver is based on the principle of
frequency to voltage conversion. The receive section is shown in fig.4 and
comprises an antialiasing prefilter, a receive amplifier, group delay
equaliser, receive filter, limiter, demodulator, post-demodulator filter
and slicer. The receive standard is set by the state of the TRS, TXR1 and
TXR2 input.
The antialiasing prefilter is a continuous low-pass filter which prevents
aliasing, due to the sampling nature of the receive filter and group delay
equaliser, of high frequency components of the input signal at RXA.
The receive amplifier is of variable gain and its purpose is to maintain a
suitable signal output level from the receive filter across the dynamic range
of the input signal at RXA.
The receive filter is designed to limit the bandwidth of the signal presented
to the demodulator, reducing out of band interference and also giving high
rejection of backward channel frequencies which are typically present at much
higher levels than the received signal.
The receive filter achieves this by taking the form of a single band-pass stage
when in 5 75 150 bauds receive mode, but in the 600 1200 bauds receive mode an
additional high-pass filter stage is placed ahead of it, thereby limiting the
effect of the frequencies corresponding to the lower bit rates.
RECEIVER
�������������Ŀ ���������Ŀ ����������������Ŀ �������������Ŀ
�ANTI-ALIASING� � RECEIVE � � � � GROUP DELAY �
RXA>�Ĵ PRE-FILTER ���>�ĴAMPLIFIER��>Ĵ RECEIVE FILTER ��>Ĵ EQUALIZER ÿ
� � �( A.G.C.)� � � � ��
��������������� ����������� ������������������ ��������������ٳ
����������������������<���������������������Ĵ
����������������������������������������������������<�����������������������
� �������Ŀ �������������Ŀ �������������Ŀ ��������Ŀ
� � � � � � POST � � �
�ĴLIMITER��>�����Ĵ DEMODULATOR ��>Ĵ DEMODULATOR ����>Ĵ- �
� � � � � � FILTER � � SLICER �����>RXD
��������� � ��������������� ��������������� �>Ĵ+ �
V ^ � � �
� RXT � TRS RXB � ����������
FIG.4.
The Group Delay Equalizer is a switched capacitor network which corrects for
both phase and attenuation distortion introduced by the line and receive
filter. The output from the Group Delay Equalizer is measured in order both to
feedback to the receive amplifier for automatic gain control and to control the
carrier detect flag (CDT).
The limiter then converts this analogue signal into a squared FSK modulated
signal which is then presented to the demodulator.
The demodulator, which is an edge triggered multivibrator, performs the
frequency to voltage conversion which allows to extract the transmitted data
from the modulated signal. The monostable triggers on both the positive and
negative going edge of the limited signal, thus producing at its output,
a stream of fixed lenght pulses at a frequency which is double that ot the
limited input signal.
The dc component of this signal is inversely proportional to the received
frequency and is extracted by a switched capacitor, low-pass, post demodulator
filter.
The output analogue signal of the post demodulator filter must be converted
into a binary signal by the slicer.
TCM 3105 PAGE 8 (4-12)
FSK MODEM
This is performed by a comparator whose reference and therefore decision
threshold is externally set, by input, to the midpoint of the analogue signal.
(The midpoint is defined as that level between the dc output level of a
continuous mark frequency and the dc output level of a continuous space
frequency).
This external adjustment on RXB also balances possible internal offsets.
(for RXB adjustment procedure see page 4-15).
The output of the comparator is then available at the RXD output.
carrier detector
The carrier detect circuitry comprises an energy detector and digital delay.
The energy detector and digital delay. The energy detector compares the total
signal level at the output of the receive filter to an externally set threshold
on the CDL pin. If there is a loss of carrier singal then CDT (carrier status
flag) will not go low during a time delay fixed by the digital delay.
If, however this fixed time has elapsed and the carrier is still not present
then CDT goes low and "carrier fail" is indicated.
The carrier detector also has a minimum 2 dbm hysteresis to avoid oscillations
on CDT when the receive level is close to the carrier detect threshold.
timing and control
An on-chip oscillator runs from an external 4.4336 MHz PAL crystal connected
between OSC1 and OSC2 or an external signal driving OSC1. A clock signal equal
to 16 times the highest selected bit rate (transmit or receive) is available on
the CSK pin.
The single supply implies that all analogue functions be referenced to an
internally generated voltage. All analogue inputs and outputs must be a.c.
coupled. or d.c. bias must be adapted.
receive/transmit modes of operations
STANDARD TRS TXR1 TXR2 TRANSMITTED RECEIVED CLK
BIT RATE (b/s) BIT RATE (b/s) FREQUENCY(KHz)
0 0 0 1200 1200 19.11
1 0 0 1200 75 19.11
0 0 1 600 75 9.56
1 0 1 600 600 9.56
CCITT V23 0 1 0 75 1200 19.11
1 1 0 75 600 9.56
0 1 1 75 75 1.19
___
CLK* 0 0 1200 1200 19.11
CLK 8 0 1 1200 150 19.11
CLK 8 0 1 1200 5 19.11
BELL202 CLK 1 0 150 1200 19.11
CLK 1 1 150 150 2.39
See note 1 1 See note 1 5 1200 19.11
1 1 1 Transmit 1200 19.11
disabled
FIG. 5
Clock output must be inverted and connected to TRS input.
NOTE 1 : In this mode the modulation is controlled by the TRS and TXR2
TRS = CLK & TXR2 = 0 TXD = 1 TXA = 387Hz
TRS = 1 & TXR2 = 1 TXD = 1 or 0, TXA = 0Hz
TCM 3105 PAGE 9 (4-13)
FSK MODEM
frequency assignment
STANDARD TRANSMITTED TXD TRANSMITTED
BIT RATE b/s FREQUENCY Hz
75 1 M 390
75 0 S 450
600 1 M 1300
CCITT V23 600 0 S 1700
1200 1 M 1300
1200 0 S 2100
150 1 M 387
150 0 S 487
1200 1 M 1200
BELL 202 1200 0 S 2200
5 See note 1 M 387
S 0
FIG.6
NOTE 1 : In this mode the modulation is controlled by the TRS and TRX2 inputs
TRS = CLK & TXR2 = 0 TXD = 1 TXA = 387 Hz
TRS = 1 & TXR2 = 1 TXD = 1 or 0 TXA = 0 Hz
TCM 3105 PAGE 10 (4-14)
FSK MODEM (4-15)
typical applications circuits
2W/4W converter for +5V single supply operation (gives maximum dynamic range
of signal on line when only +5V is available).
FIG.8, FIG.9 See 3105_8.sch, 3105_9.sch (OrCAD SDT schematic file)
important application notes
1. AUTOMATIC GAIN CONTROL
Automatic gain control will initially be set to maximum gain when no signal is
received The gain will then be reduced in steps (up to 16, it high level is
received) on each consecutive mark received.
Consequently an adjustment delay up to 11 ms should be provided by a continuous
"Mark" signal (N.B. 11 ms would be required in the case of peak voltage of
input waveform to AGC being at maximum dynamic range of AGC).
This procedure will normally be followed such that the adjustment delay occurs
along with carrier detect and precautions should be taken when deciding upon
setting up and testing method.
2. CDL APJUSTMENT
For optimum results. CDL should be adjusted to the following ratios of VDD:
min = VDD x 0 60
typ = VDD x 0.70
max = VDD x 0.80
3. RXB ADJUSTMENT PROCEDURE
The choice of d-c voltage on the RXB input (pin 7), determines the decision
threshold of the final comparator stage of the receive circuitry. Correct
adjustment is achieved by :
(i) first applying a constant mark frequency to the receiver (RXA input) for
a minimum duration of 11 ms.
(ii) Then applying a continuous 101...... pattern while RXB input voltage is
adjusted to give an RXD output signal with a 50 % duty cycle.
min = VDD x 0.45
typ = VDD x 0 55
max = VDD x 0.65
Scanned & digital remastered by HG5CDU (Lancelot) 1993.10.13.
Based on Texas Instruments Interface Circuits book
from HG5CES (Csuhi)
( More info Csuhi )